In many circuits we need to generate an internal adjustable voltage.
This circuit shows how it is possible to use a trusty old NE555 timer IC
and a bit of external circuitry to create a voltage inverter and
doubler. The input voltage to be doubled is fed in at connector K1. To
generate the stepped-up output at connector K2 the timer IC drives a
two-stage inverting charge pump circuit.
The NE555 is configured
as an astable multivibrator and produces a rectangular wave at its
output, with variable mark-space ratio and variable frequency. This
results in timing capacitor C3 (see circuit diagram) being alternately
charged and discharged; the voltage at pin 2 (THR) of the NE555 swings
between one-third of the supply voltage and two-thirds of the supply
voltage.
Voltage Inverter Circuit Using IC NE555
The output of the NE555 is connected to two voltage inverters. The
first inverter comprises C1, C2, D1 and D2. These components convert the
rectangular wave signal into a nega-tive DC level at the upper pin of
K2. The second inverter, comprising C4, C5, D3 and D4, is also driven
from the output of IC1, but uses the negative output voltage present on
diode D3 as its reference potential. The consequence is that at the
lower pin of output connector K2 we obtain a negative volt-age double
that on the upper pin.
Now let us look at the voltage feedback arrangement, which lets us
adjust this doubled negative output voltage down to the level we want.
The NE555 has a control voltage input on pin 5 (CV). Normally the
voltage level on this pin is maintained at two-thirds of the supply
voltage by internal circuitry. The voltage provides a reference for one
of the comparators inside the device. If the reference voltage on the CV
pin is raised towards the supply voltage by an external circuit, the
timing capacitor C3 in the astable multivibrator will take longer to
charge and to discharge. As a result the frequency of the rectangle wave
output from IC1 will fall, and its mark-space ratio will also fall.
The
source for the CV reference voltage in this circuit is the base-emitter
junction of PNP transistor T1. If the base volt-age of T1 is
approximately 500 mV lower than its emitter voltage, T1 will start to
conduct and thus pull the voltage on the CV pin towards the positive
supply.
In the feedback path NPN transistor T2 has the function
of a voltage level shifter, being wired in common-base configuration.
The threshold is set by the resistance of the feedback chain comprising
resistor R3 and potentiometer P1. When the emitter voltage of transistor
T2 is more than approximately 500 mV lower than its base voltage it
will start to conduct. Its collector then acts as a current sink.
Potentiometer P1 can be used to adjust the sensitivity of the negative
feedback circuit and hence the final output voltage level.Using T1 as a
voltage reference means that the circuit will adjust itself to
compensate not only for changes in load at K2, but also for changes in
the input supply voltage. If K2 is disconnected from the load the
desired output voltage will be maintained, with the oscillation
frequency falling to around 150 Hz.
A particular feature of this
circuit is the somewhat unconventional way that the NE555’s discharge
pin (pin 7) is connected to its output (pin 3). To understand how this
trick works we need to inspect the innards of the IC. Both pins are
outputs, driven by internal transistors with bases both connected (via
separate base resistors) to the emitter of a further transistor. The
collectors of the output transistors are thus isolated from one another
[1].
The external wiring connecting pins 3 and 7 together means
that the two transistors are operating in parallel: this roughly doubles
the current that can be switched to ground.The two oscilloscope traces
show how the output voltage behaves under different circumstances. The
left-hand figure shows the behaviour of the circuit with an input
voltage of 9 V and a resistive load of 470 Ω connected to the lower pin
of output connector K2. The figure on the right shows the situation with
an input voltage of 10 V and a load of 1 kΩ on the lower pin of output
connector K2. The pulse width and frequency of the rectangle wave at the
output of IC1 are automatically adjusted to compensate for the
differing conditions by the feedback mechanism built around T1 and T2.
Because
of the voltage drops across the Darlington out-put stage in the IC (2.5
V maximum) and the four diodes (700 mV each) the circuit achieves an
efficiency at full load (470 Ω between the output and ground) of
approximately 50 %; at lower loads (1 kΩ) the efficiency is about 65 %.
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