This is a simple Stand by Power Circuit diagram for Non Volatile Cmos Rams. To prevent loss of data when a CMOS RAM is switched from normal operation (Vcc = 5 volts) to stand-by mode (Vcc = VBAT) it must be ensured that the CS pin goes near the Vcc rail at all times.
Ac coupling to the chip select is made through capacitor C, breaking the dc current path between Vqq (and hence VBAT) and the decoder output. So, whatever the impedance state of the decoder in power down, the battery will provide current only for the RAM, low enough to keep the voltage at CS near to V^.
Power Circuit Diagram
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