Latch Debouncer Switch Circuit Diagram

This is a simple Latch Debouncer Switch Circuit Diagram In electronics latch is a circuit that has two stable states and can be used to store state information. Although this circuit uses a 74HC74, any CMOS variant of this flip-flop will work. IC1A acts as a true/ complement buffer. RI and R2 ensure that IC1A comes out of reset before the clock`s edge occurs. R3 applies IClA`s logic state to pins 1 and 3. When the switch closes, the next logic state stored on the capacitor transfers to the flip-flop`s reset and clock inputs. 

Latch Debouncer Switch Circuit Diagram 

Latch Debouncer Switch Circuit Diagram

Releasing the switch lets the capacitor charge to the next state via R4. IClA`s output is the LSB; IClB`s output is the MSB. Notice that the counter`s state advances when the switch is first pressed, rather than when it`s released; the latter is the case with many other switch-debouncing schemes. You can replace RI with a 22-pF capacitor to reduce the circuit`s sensitivity to parasitic effects. The addition of this capacitor also lets you lower the magnitude of R2 and R3 by a factor of 10.


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