Digital Low Input Capacitance Buffer Circuit Diagram

uses Ql and Q2 constitute a simple, high-speed FET input buffer.·Ql functions as a source follower, with the Q2 current-source load setting the drain-source channel current. The LT1010 buffer provides output drive capability for cables or whatever load is required. 

 Digital Low Input Capacitance Buffer Circuit Diagram

 Digital Low Input Capacitance Buffer Circuit Diagram

The LTC1052 stabilizes the circuit by comparing the filtered circuit output to a similarly filtered version of the input signal. The amplified difference between these signals is used to set Q2`s bias, and hence Ql`s channel current. This forces Ql`s V0 s to whatever voltage is required to match the circuit`s input and output potentials. The diode in Ql`s source line ensures that the gate never forward biases and the 2000-pF capacitor at Al provides stable loop compensation. 

The rc network in Al `s output prevents it from seeing high-speed edges coupled through Q2`s collector-base ]unction. A2`s output is also fed back to the shield around Ql `s gate lead, bootstrapping the circuit`s effective input capacitance to less than 1 pF.


Post a Comment

All updates in Your Inbox

Enter your email address:

Delivered by FeedBurner



Copyright @ 2013 Electronic Circuit Diagrams & Schematics.

Designed by AS & AS